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Rev 1; 9/03
DS1086 Spread-Spectrum EconOscillator
General Description
The DS1086 EconOscillatorTM is a programmable clock generator that produces a spread-spectrum (dithered) square-wave output of frequencies from 260kHz to 133MHz. The selectable dithered output reduces radiated-emission peaks by dithering the frequency 2% or 4% below the programmed frequency. The DS1086 has a power-down mode and an output-enable control for power-sensitive applications. All the device settings are stored in nonvolatile (NV) EEPROM memory allowing it to operate in stand-alone applications.
Features
User-Programmable Square-Wave Generator Frequencies Programmable from 260kHz to 133MHz 2% or 4% Selectable Dithered Output Glitchless Output-Enable Control 2-Wire Serial Interface Nonvolatile Settings 5V Supply No External Timing Components Required Power-Down Mode 10kHz Master Frequency Step Size EMI Reduction
DS1086
Applications
Printers Copiers PCs Computer Peripherals Cell Phones Cable Modems
Ordering Information
PART DS1086U* DS1086Z PIN-PACKAGE 8 SOP (118mil) 8 SO (150mil)
*Future Product
Typical Operating Circuit
DITHERED 260kHz TO 133MHz OUTPUT VCC N.C. OUT SPRD VCC GND DECOUPLING CAPACITORS (0.1F and 0.01F) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086 NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING. SCL* VCC
Pin Configuration
TOP VIEW
MICROPROCESSOR XTL1/OSC1 XTL2/OSC2
OUT 1 SPRD VCC 2
8 7
SCL SDA PDN OE
DS1086
SDA* PDN OE
DS1086
3 6 5 GND 4
SOP/SO
EconOscillator is a trademark of Dallas Semiconductor.
______________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
DS1086 Spread-Spectrum EconOscillator DS1086
ABSOLUTE MAXIMUM RATINGS
Voltage on VCC Relative to Ground ......................-0.5V to +6.0V Voltage on SPRD, PDN, OE, SDA, SCL Relative to Ground (See Note 1).......-0.5 to (VCC + 0.5V) Note 1: This voltage must not exceed 6.0V. Operating Temperature Range...............................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature ..................See IPC/JEDEC J-STD-020A
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = 5V 5%, TA = 0C to +70C.)
PARAMETER Supply Voltage High-Level Input Voltage (SDA, SCL) Low-Level Input Voltage (SDA, SCL) High-Level Input Voltage (SPRD, PDN, OE) Low-Level Input Voltage (SPRD, PDN, OE) SYMBOL VCC VIH VIL VIH VIL (Note 1) CONDITIONS MIN 4.75 0.7 x VCC -0.3 2 -0.3 TYP 5.00 MAX 5.25 VCC + 0.3 0.3 x VCC VCC + 0.3 0.8 UNITS V V V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V 5%, TA = 0C to +70C.)
PARAMETER High-Level Output Voltage (OUT) Low-Level Output Voltage (OUT) High-Level Input Current Low-Level Input Current Supply Current (Active) Standby Current (Power-Down) SYMBOL VOH VOL IIH IIL ICC ICCQ IOL = 4mA VCC = 5.25V VIL = 0 CL = 15pF (output at default frequency) Power-down mode -1 35 10 CONDITIONS IOH = -4mA, VCC = min MIN 2.4 0.4 1 TYP MAX UNITS V V A A mA A
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DS1086 Spread-Spectrum EconOscillator
MASTER OSCILLATOR CHARACTERISTICS
(VCC = 5V 5%, TA = 0C to +70C.)
PARAMETER Master Oscillator Range Default Master Oscillator Frequency Master Oscillator Frequency Tolerance Voltage Frequency Variation SYMBOL fOSC f0 f0 f0 fV f0 fT f0 f f0 INL VCC = 5V, TA = +25C (Notes 3,17) Over voltage range, TA = +25C (Note 4) Over temperature range, VCC = 5V (Note 5) Default frequency (f0) DAC step size Default frequency DAC step size Default frequency 133MHz 66MHz -0.75 -0.75 -0.75 -0.75 -0.5 -0.5 -1.0 2 4 -0.4 10 10.24 500 5.12 RANGE (5 LSBs of RANGE register) f0/4096 +0.4 (Note 2) CONDITION MIN 66 97.1 +0.75 % +0.75 +0.75 +0.75 +0.5 +0.5 +1.0 % % kHz MHz decimal MHz % % TYP MAX 133 UNITS MHz MHz
DS1086
Temperature Frequency Variation
Dither Frequency Range Integral Nonlinearity of Frequency DAC DAC Step Size DAC Span DAC Default Offset Step Size
Prescaler bit J0 = 1 (Note 6) Prescaler bit J0 = 0 (Note 6) Entire range (Note 7) between two consecutive DAC values (Note 8) Frequency range for one offset setting (see Table 2) Factory default register setting between two consecutive offset values (see Table 2)
Offset Default Dither Rate
OS
Factory default OFFSET register setting (5 LSBs) (see Table 2)
hex Hz
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DS1086 Spread-Spectrum EconOscillator DS1086
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V 5%, TA = 0C to +70C.)
PARAMETER Frequency Stable After Prescaler Change Frequency Stable After DAC or Offset Change Power-Up Time Enable of OUT After Exiting Power-Down Mode OUT High-Z After Entering Power-Down Mode Load Capacitance Output Duty Cycle (OUT) PDN Rise/Fall Time (Note 9) tpor + tstab (Note 10) tstab tpdn CL (Note 11) 40 15 0.2 0.1 SYMBOL CONDITION MIN TYP MAX 1 1 0.5 500 0.1 50 60 1 UNITS Period ms ms s ms pF % s
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(VCC = 5V 5%, TA = 0C to +70C.)
PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition LOW Period of SCL HIGH Period of SCL Setup Time for a Repeated START Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode CONDITION (Note 12) (Note 12) (Notes 12, 13) (Note 12) (Note 12) (Note 12) (Notes 12, 14, 15) (Note 12) (Note 16) (Note 16) 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 100 250 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.9 MIN TYP MAX 400 100 UNITS kHz s s s s s s ns 300 1000 300 1000 ns ns
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DS1086 Spread-Spectrum EconOscillator
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (continued)
(VCC = 5V 5%, TA = 0C to +70C.)
PARAMETER Setup Time for STOP Capacitive Load for Each Bus Line NV Write-Cycle Time Input Capacitance SYMBOL tSU:STO CB tWR CI 5 Fast mode Standard mode (Note 16) CONDITION MIN 0.6 4.0 400 10 TYP MAX UNITS s pF ms pF
DS1086
Note 1: Note 2: Note 3: Note 4: Note 5:
Note 6: Note 7: Note 8: Note 9: Note 10:
Note 11: Note 12:
Note 13: Note 14: Note 15: Note 16: Note 17:
All voltages are referenced to ground. DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range. Correct operation of the device is not guaranteed if these limits are exceeded. This is the absolute accuracy of the master oscillator frequency at the default settings. This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at TA = +25C. This is the percentage frequency change from the +25C frequency due to temperature at VCC = 5V. The maximum temperature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequency (fdefault). The maximum occurs at the extremes of the master oscillator frequency range (66MHz or 133MHz) (see Figure 2). The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency. The integral nonlinearity of the frequency adjust DAC is a measure of the deviation from a straight line drawn between the two endpoints of a range. The error is in percentage of the span. This is true when the prescaler = 1. Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original value to the new value. This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 512 master clock cycles and therefore depends on the programmed clock frequency. Output voltage swings can be impaired at high frequencies combined with high output loading. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least tR MAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. CB--total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Typical frequency shift due to aging is 0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr +125C bake, 168hr 85C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5C peak) followed by 1000hr max VCC biased 125C HTOL, 1000 temperature cycles at -55C to +125C, 96hr 130C/85%RH/5.5V HAST and 168hr 121C/2 ATM Steam/Unbiased Autoclave.
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DS1086 Spread-Spectrum EconOscillator DS1086
Typical Operating Characteristics
(VCC = 5.0V, TA = 25C, unless otherwise noted)
SUPPLY CURRENT vs. TEMPERATURE
DS1086 toc01
SUPPLY CURRENT vs. VOLTAGE
DS1086 toc02
SUPPLY CURRENT vs. PRESCALER
19 18 17 CURRENT (mA) 16 15 14 13 12 11 10 4.75V 5.0V
DS1086 toc03
20 19 18 17 CURRENT (mA) 16 15 14 13 12 11 10 0 10 20 30 40 50 60
20 19 18 17 CURRENT (mA) 16 15 14 13 12 11 10
20
5.25V
70
4.75
4.85
4.95
5.05
5.15
5.25
0
50
100
150
200
250
TEMPERATURE (C)
VOLTAGE (V)
PRESCALER
SUPPLY CURRENT vs. PRESCALER
DS1086 toc04
SUPPLY CURRENT vs. TEMPERATURE WITH OE = 0
DS1086 toc05
SUPPLY CURRENT vs. TEMPERATURE WITH PDN = 0
9 8 7 CURRENT (A) 6 5 4 3 2 1 0
DS1086 toc06
20 19 18 17 CURRENT (mA) 16 15 14 13 12 11 10 0 50 100 150 200 70C, 25C, AND 0C
10 9 8 7 CURRENT (mA) 6 5 4 3 2 1 0
10
250
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
PRESCALER
TEMPERATURE (C)
TEMPERATURE (C)
FREQUENCY PERCENT CHANGE vs. SUPPLY VOLTAGE
DS1086 toc07
FREQUENCY PERCENT CHANGE vs. TEMPERATURE
FREQUENCY PERCENT CHANGE FROM 25C 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 10 20 30 40 50 60 70
DS1086 toc08
1.0 FREQUENCY PERCENT CHANGE FROM 5V 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 4.75 4.85 4.95 5.05 5.15
1.0
5.25
VOLTAGE (V)
TEMPERATURE (C)
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DS1086 Spread-Spectrum EconOscillator
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME OUT SPRD VCC GND OE PDN SDA SCL Oscillator Output Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled. Power Supply Ground Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is disabled but the master oscillator is still on. Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master oscillator is disabled (power-down mode). 2-Wire Serial Data. This pin is for serial data transfer to and from the device. The pin is open drain and can be wire-OR'ed with other open-drain or open-collector interfaces. 2-Wire Serial Clock. This pin is used to clock data into the device on rising edges and clock data out on falling edges. FUNCTION
DS1086
CLOCK SPECTRUM COMPARISON (9kHz BW, PEAK DETECT)
DS1086 fig01
MAXIMUM TEMPERATURE VARIATION vs. MASTER FREQUENCY
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 66.00 82.75 99.50 116.25 133.00
DS1086 fig02
0 -5 RELATIVE AMPLITUDE (dBm) -10 -15 DS1086 4% DITHER -20 -25 -30 -35 -40 90 91 92 93 94 CRYSTAL OSC DS1086 NO DITHER
2.0 FREQUENCY % CHANGE FROM 25C
95
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 1. Clock Spectrum Dither Comparison
Figure 2. Temperature Variation Over Frequency
Processor-Controlled Mode
VCC MICROPROCESSOR 4.7k XTL1/OSC1 XTL2/OSC2 OUT SPRD VCC GND DECOUPLING CAPACITORS (0.1F and 0.01F) SCL SDA 2-WIRE INTERFACE N.C.
Stand-Alone Mode
DITHERED 260kHz TO 133MHz OUTPUT VCC OUT SPRD VCC GND DECOUPLING CAPACITORS (0.1F and 0.01F) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086 NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING. SCL* VCC
DITHERED 260kHz TO 133MHz OUTPUT VCC
4.7k
DS1086
SDA* PDN OE
DS1086
PDN OE
VCC
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DS1086 Spread-Spectrum EconOscillator DS1086
Table 1. Register Summary
REGISTER PRESCALER DAC HIGH DAC LOW OFFSET ADDR RANGE WRITE EE ADDR 02h 08h 09h 0Eh 0Dh 37h 3Fh MSB X1 b9 b1 X1 X1 XX X1 b8 b0 X1 X1 XX XX b7 X0 X1 X1 XX BINARY J0 P3 b6 b5 X0 X0 b4 b3 X1 WC b4 b3 NO DATA P2 b4 X0 b2 A2 b2 P1 b3 X0 b1 A1 b1 LSB P0 b2 X0 b0 A0 b0 FACTORY DEFAULT 11100000b 01111101b 00000000b 111- ----b 11110000b xxx- - - - - b
--
ACCESS R/W R/W R/W R/W R/W R
--
X0 = Don't care, reads as zero. X1 = Don't care, reads as one. XX = Don't care, reads indeterminate. X = Don't care.
Table 2. Offset Settings
OFFSET OS - 6 OS - 5 OS - 4 OS - 3 OS - 2 OS - 1 OS* OS + 1 OS + 2 OS + 3 OS + 4 OS + 5 OS + 6 FREQUENCY RANGE (MHz) 61.44 to 71.67 66.56 to 76.79 71.68 to 81.91 76.80 to 87.03 81.92 to 92.15 87.04 to 97.27 92.16 to 102.39 97.28 to 107.51 102.40 to 112.63 107.52 to 117.75 112.64 to 122.87 117.76 to 127.99 122.88 to 133.11
*Factory default setting. OS is the integer value of the 5 LSBs of the RANGE register.
Detailed Description
A block diagram of the DS1086 is shown in Figure 3. The internal master oscillator generates a square wave with a 66MHz to 133MHz frequency range. The frequency of the master oscillator can be programmed with the DAC register over a two-to-one range in 10kHz steps. The master oscillator range is larger than the range possible with the DAC step size, so the OFFSET register is used to select a smaller range of frequencies over which the DAC spans. The prescaler can then be set to divide the master oscillator frequency by 2 x
(where x equals 0 to 8) before routing the signal to the output (OUT) pin. A programmable triangle-wave generator injects an offset element into the master oscillator to dither its output 2% or 4%. The dither is controlled by the J0 bit in the PRESCALER register and enabled with the SPRD pin. The maximum spectral attenuation occurs when the prescaler is set to 1. The spectral attenuation is reduced by 2.7dB for every factor of 2 that is used in the prescaler. This happens because the prescaler's divider function tends to average the dither in creating the lower frequency. However, the most stringent spectral emission limits are imposed on the higher frequencies where the prescaler is set to a low divider ratio. The external control input, OE, gates the clock output buffer. The PDN pin disables the master oscillator and turns off the clock output for power-sensitive applications*. On power-up, the clock output is disabled until power is stable and the master oscillator has generated 512 clock cycles. Both controls feature a synchronous enable that ensures there are no output glitches when the output is enabled, and a constant time interval (for a given frequency setting) from an enable signal to the first output transition. The control registers are programmed through a 2-wire interface and are used to determine the output frequency and settings. Once programmed into EEPROM, since the register settings are NV, the settings only need to be reprogrammed if it is desired to reconfigure the device.
*The power-down command must persist for at least two output frequency cycles plus 10s for deglitching purposes.
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DS1086 Spread-Spectrum EconOscillator DS1086
VCC EEPROM CONTROL REGISTERS DAC OFFSET ADDR RANGE PRESCALER FREQUENCY CONTROL VOLTAGE DAC
SDA SCL
DS1086
2-WIRE INTERFACE
PDN
VOLTAGE-CONTROLLED OSCILLATOR MASTER OSCILLATOR OUTPUT PRESCALER BY 1, 2, 4...256 OUT
DITHER CONTROL
OE SPRD GND TRIANGLE WAVE GENERATOR
DITHER SIGNAL
Figure 3. DS1086 Block Diagram
The output frequency is determined by the following equation:
fOUTPUT =
(MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC VALUE x 10 kHz STEP SIZE) PRESCALER
PRESCALER Register
The PRESCALER register controls the prescaler (bits P3 to P0) and dither (bit J0). The prescaler divides the master oscillator frequency by 2x where x can be from 0 to 8. Any prescaler value entered that is greater than 8 decodes as 8. The dither applied to the output is controlled with bit J0. When J0 is high, 2% peak dither is selected. When J0 is low, 4% peak dither is selected.
(1) where: min frequency of selected OFFSET range is the lowest frequency (shown in Table 2 for the corresponding offset). DAC value is the value of the DAC register (0 to 1023). Prescaler is the value of 2x where x = 0 to 8. See the Example Frequency Calculations section for a more in-depth look at using the registers.
DAC HIGH/DAC LOW Register
The 2-byte DAC register sets the frequency of the master oscillator to a particular value within the current offset range. Each step of the DAC changes the master oscillator frequency by 10kHz. The first byte is the MSB (DAC HIGH) and the second byte is the LSB (DAC LOW).
________________Register Definitions
The DS1086 registers are used to determine the output frequency and dither amount. A summary of the registers is shown in Table 1. Using the default register settings below, the default output frequency is 97.1MHz. See the Example Frequency Calculations section for an example on how to determine the register settings for a desired output frequency.
OFFSET Register
The OFFSET register determines the range of frequencies that can be obtained for a given DAC setting. The factory default offset is copied into the RANGE register so the user can access the default offset after making changes to the OFFSET register. See Table 2 for OFFSET ranges. Correct operation of the device is not guaranteed outside the range 66MHz to 133MHz.
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DS1086 Spread-Spectrum EconOscillator DS1086
ADDR Register
The A0, A1, A2 bits determine the 2-wire slave address. The WC bit determines if the EEPROM is to be written to after register contents have been changed. If WC = 0 (default), EEPROM is written automatically after a WRITE EE command. If WC = 1, the EEPROM is only written when the WRITE EE command is issued. In applications where the register contents are frequently written, the WC bit should be set to 1. Otherwise, it is necessary to wait for an EEPROM write cycle to complete between writing to the registers. This also prevents wearing out the EEPROM. Regardless of the value of the WC bit, the value of the ADDR register is always written immediately to EEPROM. When the WRITE EE command has been received, the contents of the registers are written into the EEPROM, thus locking in the register settings. equals 0 to 8 (and x is the value that is programmed into the P3 to P0 bits of the PRESCALER register). Equation 1 shows the relationship between the desired frequency, the master oscillator frequency, and the prescaler.
f fDESIRED = MASTER OSCILLATOR prescaler fMASTER OSCILLATOR 2X =
(2)
RANGE Register
This read-only register contains a copy of the factoryset offset (OS). This value can be read to determine the default value of the OFFSET register when programming a new master oscillator frequency.
By trial and error, x is incremented from 0 to 8 in Equation 2, finding values of x that yield master oscillator frequencies within the range of 66MHz to 133MHz. Equation 2 shows that a prescaler of 8 (x = 3) and a master oscillator frequency of 88.4736MHz generates our desired frequency. In terms of the device register, x = 3 is programmed in the lower four bits of the PRESCALER register. Writing 03h to the PRESCALER register sets the PRESCALER to 8 (and 4% peak dither). Be aware that the J0 bit also resides in the PRESCALER register.
fMASTER OSCILLATOR = fDESIRED x prescaler = fDESIRED x 2X fMASTER OSCILLATOR = 11.0592MHz x 23 = 88.4736MHz (3) Once the target master oscillator frequency has been calculated, the value of offset can be determined. Using Table 2, 88.4736MHz falls within both OS - 1 and OS - 2. However, choosing OS - 1 would be a poor choice since 88.4736MHz is so close to OS - 1's minimum frequency. On the other hand, OS - 2 is ideal since 88.4736MHz is very close to the center of OS - 2's frequency span. Before the OFFSET register can be programmed, the default value of offset (OS)
WRITE EE Command
This command is used to write data from RAM to EEPROM when the WC bit in ADDR register is 1. See the ADDR Register section for more details.
Example Frequency Calculations
Example #1: Calculate the register values needed to generate a desired output frequency of 11.0592MHz. Since the desired frequency is not within the valid master oscillator range of 66MHz to 133MHz, the prescaler must be used. Valid prescaler values are 2x where x
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 4. 2-Wire Data Transfer Protocol 10 ____________________________________________________________________
DS1086 Spread-Spectrum EconOscillator
must be read from the RANGE register (last five bits). In this example, 12h (18 decimal) was read from the RANGE register. OS - 2 for this case is 10h (16 decimal). This is the value that is written to the OFFSET register. Finally, the two-byte DAC value needs to be determined. Since OS - 2 only sets the range of frequencies, the DAC selects one frequency within that range as shown in Equation 3.
fMASTER OSCILLATOR = (MIN FREQUENCY OF SELECTED OFFSET
RANGE) + (DAC value x 10kHz)
The expected output frequency is not exactly equal to the desired frequency of 11.0592MHz. The difference is 450Hz. In terms of percentage, Equation 6 shows that the expected error is 0.004%. The expected error assumes typical values and does not include deviations from the typical as specified in the electrical tables.
fDESIRED - fEXPECTED x 100 fDESIRED
DS1086
%ERROREXPECTED =
(6)
Valid values of DAC are 0 to 1023 (decimal) and 10kHz is the step size. Equation 4 is derived from rearranging Equation 3 and solving for DAC.
%ERROREXPECTED =
11.0592MHz - 11.05875MHz 11.0592MHz 450Hz x 100 = x 100 = 0.004% 11.0592MHz
DAC VALUE =
(fMASTER OSCILLATOR - MIN FREQUENCY OF SELECTED OFFSET RANGE) 10kHz STEP SIZE
Example #2: Calculate the register values needed to generate a desired output frequency of 100MHz. Since the desired frequency is already within the valid master oscillator frequency range, the prescaler is set to divide by 1, and hence, PRESCALER = 00h (for 4% peak dither) or 10h (for 2% peak dither). (7) (4)
fMASTER OSCILLATOR = 100.0MHz x 20 = 100.0MHz
DAC VALUE =
(88.4736MHz - 81.92MHz) 10kHz STEP SIZE = 655.36 655 (decimal)
Since the two-byte DAC register is left justified, 655 is converted to hex (028Fh) and bit-wise shifted left six places. The value to be programmed into the DAC register is A3C0h. In summary, the DS1086 is programmed as follows: PRESCALER = 03h (4% peak dither) or 13h (2% peak dither) OFFSET = OS - 2 or 10h (if range was read as 12h) DAC = A3C0h Notice that the DAC value was rounded. Unfortunately, this means that some error is introduced. In order to calculate how much error, a combination of Equation 1 and Equation 3 is used to calculate the expected output frequency. See Equation 5.
(MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC VALUE x 10kHz STEP SIZE) fOUTPUT = prescaler (81.92MHz) + (655 x 10kHz) fOUTPUT = = 8 88.47MHz = 11.05875MHz 8
Next, looking at Table 2, OS + 1 provides a range of frequencies centered around the desired frequency. In order to determine what value to write to the OFFSET register, the RANGE register must first be read. Assuming 12h was read in this example, 13h (OS + 1) is written to the OFFSET register. Finally, the DAC value is calculated as shown in Equation 8. (8)
DAC VALUE = (100.0MHz - 97.28MHz) = 272.00 (decimal) 10kHz STEP SIZE
The result is then converted to hex (0110h) and then left-shifted, resulting in 4400h to be programmed into the DAC register. In summary, the DS1086 is programmed as follows: PRESCALER = 00h (4% peak dither) or 10h (2% peak dither) OFFSET = OS + 1 or 13h (if RANGE was read as 12h) DAC = 4400h (9)
(5)
fOUTPUT
=
(97.28MHz) + (272 x 10kHz)
= 20 100.0MHz = 100.0MHz 1
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DS1086 Spread-Spectrum EconOscillator DS1086
MSB 1 0 1 1 A2 A1 A0
LSB R/W
Figure 5. Slave Address
SDA
tBUF tLOW tR tF
REA
D/W
RIT EB
DEVICE IDENTIFIER
DEVICE ADDRESS
IT
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 6. 2-Wire AC Characteristics
Since the expected output frequency is equal to the desired frequency, the calculated error is 0%.
_______2-Wire Serial Port Operation
2-WIRE SERIAL DATA BUS
The DS1086 communicates through a 2-wire serial interface. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a "master." The devices that are controlled by the master are "slaves." A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1086 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (see Figures 4 and 6): * Data transfer can be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.
*
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DS1086 Spread-Spectrum EconOscillator
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1086 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. When the DS1086 EEPROM is being written to, it is not able to perform additional responses. In this case, the slave DS1086 sends a not acknowledge to any data transfer request made by the master. It resumes normal operation when the EEPROM operation is complete. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figures 4, 5, 6, and 7 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1086 can operate in the following two modes: Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1086 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
DS1086
Slave Address
Figure 5 shows the first byte sent to the device. It includes the device identifier, device address, and the R/W bit. The device address is determined by the ADDR register.
Registers/Commands
See Table 1 for the complete list of registers/commands and Figure 7 for an example of using them.
__________Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1086, decouple the power supply with 0.01F and 0.1F high-quality, ceramic, surface-mount capacitors. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. These capacitors should be placed as close to pins 3 and 4 as possible.
Stand-Alone Mode
SCL and SDA cannot be left floating when they are not used. If the DS1086 never needs to be programmed incircuit, including during production testing, SDA and SCL can be tied high. The SPRD pin must be tied either high or low.
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13
DS1086 Spread-Spectrum EconOscillator DS1086
TYPICAL 2-WIRE WRITE TRANSACTION MSB START 1 0 1 1 LSB A2* A1* A0* R/W DEVICE ADDRESS READ/ WRITE SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
DEVICE IDENTIFIER
COMMAND/REGISTER ADDRESS
DATA
EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO) B0h 0Eh SLAVE SLAVE A) SINGLE BYTE WRITE START 1 0 1 1 0 0 0 0 ACK 0 0 0 0 1 1 1 0 ACK -WRITE OFFSET REGISTER B0h B) SINGLE BYTE READ -READ OFFSET REGISTER START 1 0 1 1 0 0 0 0 0Eh SLAVE SLAVE 00001110 ACK ACK
DATA OFFSET SLAVE ACK B1h REPEATED START DATA DAC MSB SLAVE ACK B1h REPEATED START 10110001 SLAVE ACK 10110001 SLAVE ACK DATA DAC LSB SLAVE ACK DATA DAC MSB MASTER ACK STOP STOP
DATA OFFSET MASTER NACK STOP
C) TWO BYTE WRITE -WRITE DAC REGISTER
B0h 08h START 1 0 1 1 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 SLAVE ACK ACK B0h 08h START 1 0 1 1 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 SLAVE ACK ACK
DATA DAC LSB MASTER NACK STOP
D) TWO BYTE READ -READ DAC REGISTER
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST MATCH THE ADDRESS SET IN THE ADDR REGISTER.
Figure 7. 2-Wire Transactions
Chip Topology
TRANSISTOR COUNT: 10,000 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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